1. Field of the Invention
This invention relates to a data transmission apparatus principally performing data transmission between systems making asynchronous operations, and further to be detailed, relates to a data transmission apparatus capable of controlling transmission of data corresponding to the state of sending data on the side of the system outputting the data.
2. Description of the Prior Art
Conventionally, for a data transmission apparatus, for example, the data transfer control circuit of FIFO (First-In First-Out) memory has been known. As an example thereof, FIG. 1 shows a configuration of an asynchronous FIFO memory as shown in "The Bipolar Digital Integrated Circuits Data Book for Design Engineer Part 2" (TEXAS INSTRUMENTS, 1982, Vol. 17, p61).
In this example, two-stage latches are used. This means that numerals 42 and 43 in the figure designate data latches, which are connected by a four-bit data line. Also, numerals 44 and 45 designate control circuits, and the control circuit 44 controls the data latch 42 and the control circuit 45 controls the data latch 43, respectively.
Numeral 46 designates a one-shot pulse circuit using a D-flip-flop, and when a high active reset signal RESET is low ("0"), that is, where a high-level write request pulse signal (data transfer request signal) "PUSH" is given when the high level ("1") is given to a data terminal D, a high-level SEND signal (data transfer request signal) S1 is outputted from an output terminal Q thereof.
This SEND signal S1 is given to the data latch 42 as a high-level signal L1 and is transmitted to the control circuit 45 of the next stage as a SEND signal S2.
The data latch 42 is given the high-level signal L1, and thereby latches a data D1 given from the preceding stage side, and outputs it to the data latch 43 of the following stage side as a data D2.
The high-level SEND signal S2 given to the control circuit 45 is given to the data latch 43 as a high-level signal L2, and is further given to a control circuit (not illustrated) of the following stage as a high-level SEND signal S3.
The data latch 43 is given the high-level signal L2, and thereby latches the data D2 from the data latch 42 of the preceding stage, and further outputs it to the following stage as a data D3.
Accordingly, as shown in FIG. 2, a data constituted with a word 1 and a word 2 is transmitted in the sequence of the data latches 42, 43.
Then, in such a conventional data transmission apparatus, the number of stages of data latches is fixed and does not vary during data transmitting operation, and therefore the time required for transmitting data to be transmitted is constant irrespective of the amount of the data. Accordingly, the following problems are raised in the case where the data transmission apparatus as described above is used for data transmission between two systems performing asynchronous operation.
(1) In the case where the number of stages of the FIFO memory is large, when the amount of data to be transmitted between two systems is small, a long time is required for data transmission in comparison with the amount of data.
(2) In the case where the number of stages of the FIFO memory is small, when the amount of data to be transmitted between two systems is large, a non-smooth flow of data caused by asynchronous operations cannot be buffer-stored, resulting in an overflow.